1. Field of the Invention
The present invention is directed to logic devices and, in particular, to a differential input receiver.
2. Background Information
Integrated circuit technology today is quickly moving from 0.20 micron technology to 0.17 micron technology and movement to 0.13 micron technology is anticipated in the near future. As a result, operating voltages for transistors in the integrated circuits is decreasing. As operating voltages decrease, the maximum allowed voltage that the gate of a transistor in a logic circuit decreases as well. This is due to the gate oxide voltage (oxide stress) that can be withstood by the thin gate devices commonly used.
Thin gates and concomitant limiting gate oxide voltages can be troublesome, particularly when trying to interface a high-voltage device to a low-voltage device. For example, many input/output (I/O) devices are 3.3V LVTTL compatible I/O circuits fabricated in a 2.5V CMOS technology. Voltages across the gate oxides of these devices should not exceed 3.6V. During power up, however, the voltages across the gate oxides of these devices may exceed 3.6V.
There are several existing techniques to protect gate oxides from exceeding predetermined voltage levels. One technique is described in John Connor et al., in “Dynamic Dielectric Protection for I/O Circuits Fabricated in a 2.5V CMOS Technology Interfacing to a 3.3V LVTTL Bus,” in 1997 Symposium on VLSI Circuits Digest of Technical Papers, pages 119-120. Another technique is described in Gajendra P. Singh et al., “High-Voltage-Tolerant I/O Buffers with Low-Voltage CMOS Process,” in IEEE Journal of Solid-State Circuits, Vol., 34, No. 11, November 1999, pages 1512-1525. Hector Sanchez et al., offers another technique in “A Versatile 3.3/2.5/1.8-V CMOS I/O Driver Built in a 0.2-μm Tox, 1.8-V CMOS Technology,” in IEEE Journal of Solid-State Circuits, Vol., 34, No. 11, November 1999, pages 1501-1511. According to these techniques, devices (i.e., transistors) are stacked or cascaded in such a way that at any point in time the voltage across the gate oxides of the devices never exceeds process tolerance. These techniques apply to single ended receivers, however, and only provide static protection.